The present invention generally relates to semiconductor integrated circuits, and more particularly, to image transfer processes employing an extreme ultraviolet (EUV) sensitive lithographic structure and double patterning process.
The back-end-of-line (BEOL) is the second portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resistors, etc.) are interconnected with interconnects and a metallization layer, which function as the wiring network of the wafer. Common metals that are used to form the metallization layers and interconnects are copper and aluminum. BEOL generally begins when the first layer of metal (M1) is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. Double patterning processes such as self-aligned double patterning (SADP) or litho-etch-litho etch (LELE) are typically part of the BEOL process for advanced design rules.
Patterning at 10 nm and sub-10 nm technology nodes is a challenge for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements at these technology nodes. EUV lithography based patterning is being considered as a serious candidate for the sub-10 nm nodes.